The present invention relates to a field emitter array (FEA) and method for manufacturing the same, and more particularly, to a novel field emitter array having a shallow junction, and a method for manufacturing the same.
In response to a rapidly increasing demand for spacesaving, personal displays which serve as the primary information transmission interface between humans and computers (and other types of computerized devices), various types of flat screen or flat panel displays have been developed to replace conventional display devices, particularly CRTs, which are relatively large, bulky, and obtrusive. Examples of these flat panel displays include a plasma display, liquid crystal display, fluorescent display and field emission display. Among the flat panel displays, the field emission display has been under active research, since it can be driven by a relatively low power and can easily embody color images.
The field emission display emits electrons by a field emitter array on which the cathode tips (each of which is the source of the electrical field per a unit pixel) are highly integrated, and the emitted electrons are captured on the fluorescent layer to thereby form a pixel.
The cathode tips are arranged in a closed and limited space which is maintained at a high vacuum state for enabling the electrons to be emitted easily. The cathode tips have been mainly manufactured using a metal. In recent years, there have been suggested a number of methods for manufacturing micro-tips using developments in semiconductor manufacturing technology.
For example, Smith et al. have suggested a field emission cathode structure and manufacturing method thereof by using a single crystalline semiconductor substrate, in U.S. Pat. No. 3,970,887. Also, Greene et al. have suggested an FEA having a pyramidal field emission cathode structure on a single crystalline substrate by using a p-n junction structure, in U.S. Pat. No. 4,513,308.
FIG. 1 is a cross-sectional view of the FEA disclosed by Greene et al.
Referring to FIG. 1, an insulation layer 22 having multiple pin holes is formed in a matrix pattern on a p-type semiconductor substrate 14, and an n-type pyramidal tip 16 including the p-type semiconductor substrate 14 and a p-n junction 18 is formed in the pin holes. Here, a metallic electrode 20 is formed on the insulation layer 22, and a lower electrode 28 is provided in the lower portion of semiconductor substrate 14. When a voltage 26 is applied through the metallic electrode 20 and the lower electrode 28 so that the p-n junction may be forward biased, a predetermined amount of electrons are emitted from a tip depending on the applied voltage 26. The emitted electrons are captured in a fluorescent layer (not shown), and the fluorescent layer is excited to then form a pixel.
Most current research is concentrated on a field emission device using sharp tips by which the field emission device can operate in a high voltage emission and high-temperature environment with minimal power loss. However, the device requires high applied voltages.
Meanwhile, a method for manufacturing a field emission device has been recently proposed, which can emit electrons with low applied voltages by using a shallow silicon p-n junction region without tips (see Jung Y. Ea et al., "Silicon Avalanche Cathodes and Their Characteristics," IEEE Transactions on Electron Devices, Vol. 38, No. 10, October 1991). According to the referenced thesis, electrons are emitted through an n.sup.+ shallow junction region by a tunneling effect. However, when an FEA is manufactured by this method, after forming an opening by a patterning method, impurities are implanted therein to form a shallow junction region, which complicates the manufacturing process. Moreover, in the case of manufacturing a cathode array in which multiple field emission devices are integrated, it is difficult to manufacture such devices so as to have consistent characteristics on a single substrate.